Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■PCMCIA (JEIDA) socket control
Target PC-98HA, PC-9801P/NX/C, PC-9821Ne
Chip MECIA
Explanation o MECIA, the PC-9800 series' own PCMCIA controller, is equipped
with a mechanism to convert the I/O ports used by the card in order to use PC
cards for IBM PC/AT compatible machines.
o Basic address conversion mode can be used when the number of I/O ports used
by the card is 16 or less. The card's I/O ports can be assigned to 16
consecutive bytes in the CPU's I/O space.
o Extended address conversion mode can be used when the number of I/O ports
used by the card is 128 or less. The card's I/O ports will appear in 8
locations, 16 bytes each, in the CPU's I/O space.
Figure: Basic address conversion
--------------------------------+------------------------------------
I/O address accessed by CPU | XXXX XXXX XXXX AAAA
| ｜
| ｜
I/O address output to card | YYYY YYYY YYYY AAAA
--------------------------------+------------------------------------
* The value of XXXX XXXX XXXX ???? can be set arbitrarily in I/O 4A8Eh
Normally, SSDRV.SYS sets the user-open I/O area of I/O ??D?h
* The value of YYYY YYYY YYYY ???? can be set arbitrarily in I/O 5A8Eh
Figure: Extended address conversion
--------------------------------+------------------------------------
I/O address accessed by CPU | XXXX XBBB XXXX AAAA
| ＼ ｜
| ＼ ｜
I/O address output to card | YYYY YYYY YBBB AAAA
--------------------------------+------------------------------------
* The value of XXXX X??? XXXX ???? can be set arbitrarily in I/O Can be set
arbitrarily with 4A8Eh
Usually SSDRV.SYS sets the user open I/O area of I/O ??D?h
* The value of YYYY YYYY Y??? ???? can be set arbitrarily with I/O 5A8Eh
Table: I/O port list
------------+-------+---+-------------------------------------------
I/O address | Width |R/W| Name
------------+-------+---+-------------------------------------------
0A8Eh | BYTE |R/W|PCMCIA socket selection
1A8Eh | BYTE |R/W|PCMCIA socket status
2A8Eh | BYTE |R/W|PCMCIA various controls
3A8Eh | BYTE |R/W|IRQ level setting
4A8Eh | BYTE |R/W|PC card I/O projected address setting
5A8Eh | BYTE |R/W|PC card I/O address setting
6A8Eh | BYTE |R/W|Unknown
7A8Eh | BYTE |R/W|PC card power status
8A8Eh | BYTE |R/W|PCMCIA socket control
0E8Eh | WORD |R/W|Page address specification
------------+-------+---+-------------------------------------------
I/O 0A8Eh
Name PCMCIA socket selection
Undocumented
Function
[READ/WRITE]
Bit 7-4: Unused (always set to 0)
Bit 3-0: Socket number
* Usually set to 000b
Explanation o Selects a PCMCIA socket.
o For models without PCMCIA, this I/O port always returns FFh, so it can be
used to determine whether the model is equipped with PCMCIA. However, FFh is
also returned for models equipped with PCMCIA controllers other than MECIA3.
Related
I/O 1A8Eh
Name PCMCIA socket status
Undocumented
Function
[READ/WRITE]
Bit 7-4: Unknown
Bit 3: Card presence/absence
1 = Present
0 = Not present
Bit 2: Write protection
1 = Present
0 = Not present, no card
* Valid when bit 3 is 1.
Bit 1: RAM/ROM card identification
1 = RAM/ROM card
0 = Other
* Valid when bit 5=0 (after card identification)
Bit 0: EMS card identification
1 = EMS card
0 = Other
Description o Gets various statuses of PCMCIA sockets.
Related
I/O 2A8Eh
Name PCMCIA various controls
Undocumented
Function
[READ/WRITE]
bit 7: I/F type selection
1 = I/O interface
0 = Memory interface
bit 6: Address translation mode
1 = Address through mode (does not translate I/O port addresses)
0 = Address translation mode
bit 5: Bus width
1 = 8-bit bus mode
0 = 16-bit bus mode
bit 4: Address translation method
1 = Extended address translation method
0 = Basic address translation method
bit 3: Unknown
bit 2: PC card RDY/BSY signal
0 = Memory card READY state
1 = Memory card BUSY state
bit 1: Vcc voltage request to PC card
1 = 3.3V
0 = 5.0V
* Notifies the card of the operating voltage required by the CPU
bit 0: PC card Vcc voltage response
1 = 3.3V
0 = 5.0V
* Returns the voltage at which the card actually operates.
Description o Sets the interface with the PC card.
o Sets the power supply voltage supplied to the PC card.
Related
I/O 3A8Eh
Name IRQ level setting
Undocumeted
Function
[READ/WRITE]
Bit 7-3: Unused
Bit 2-0: IRQ level setting
000b = INT0(IRQ3
001b = INT1(IRQ5)
010b = INT2(IRQ6)
011b = Cannot be set
100b = INT4(IRQ10)
101b = INT5(IRQ12)
110b = Cannot be set
111b = No interrupts used
Explanation o Sets which IRQ level to assign to the PC card interrupt.
o Must be set so as not to conflict with interrupts used in the main unit or on expansion boards.
Related I/O 0002h
I/O 000Ah
I/O 4A8Eh
Name PC card I/O projection address setting
Undocumented
Function
[READ/WRITE]
bits 15-0: I/O address to which the PC card's I/O port is projected
Explanation o When converting the I/O address, set which I/O port on the main
unit the PC card's I/O port set in I/O 5A8Eh is projected to. Set the lower 4 bits to 0000b.
Normally, the lower 8 bits are set to D0h (user-open I/O area).
o It is necessary to set it so that it does not conflict with I/O addresses
used inside the main unit or on expansion boards.
o When in extended address conversion mode, set bits 11-8, 3-0 to 0.
Related INT 1Fh - Function CF01h
I/O 2A8Eh
I/O 5A8Eh
I/O 5A8Eh
Name PC card I/O address setting
Undocumented
Function
[READ/WRITE]
Bits 15-0: PC card I/O address
Explanation o When converting the I/O address, set the base address of the I/O
port of the PC card to be projected to the I/O address set in I/O 4A8Eh. The
I/O address specified here is output to the PC card.
o When in basic address conversion mode, set the lower 4 bits to 0000b.
o When in extended address conversion mode, set the lower 7 bits to 0000000b.
Related INT 1Fh - Function CF01h
I/O 2A8Eh
I/O 4A8Eh
I/O 6A8Eh
Name Unknown
Undocumented
Function
[READ/WRITE]
Bit 15-0: Unknown
Explanation o Details unknown
I/O 7A8Eh
Name PC card power status
Undocumented
Function
[READ/WRITE]
Bit 7: PC card BVD1 signal
1 = PC card battery depletion (data not guaranteed)
0 = Normal
Bit 6: PC card BVD2 signal
1 = PC card battery depletion (data guaranteed)
0 = Normal
Bit 5: Attribute/common selection
1 = Attribute memory
0 = Common memory
Bit 4: PC card Vpp voltage control
1 = 12V
0 = 5.0V
Bit 3,2: Unused
Bit 1: Card access
1 = Card being accessed
0 = Card not being accessed
bit 0: Low battery LED
1 = LED ON
0 = LED OFF
* Controls the card's LOW battery LED.
Explanation o After changing the power supply voltage, a wait of about 180μsec is required.
Related I/O 2A8Eh
I/O 8A8Eh
Name PCMCIA socket control
Undocumented
Function
[READ/WRITE]
Bit 7-4: Unused
Bit 3: Card presence
1 = Present
0 = Absent
* READ only
Bit 2: Unused
Bit 1: PCMCIA controller reset
1 = Reset
0 = Do not reset
Bit 0: Unused
Explanation o Resets the PCMCIA controller.
o Checks whether a PC card is inserted.
Related
I/O 0E8Eh
Name Page address setting
Undocumented
Function
[READ/WRITE]
Bit 15-0: Page address to project to DA00h bank
Explanation o Selects the page to project in the JEIDA window in 8KB units.
o This I/O is also used to specify the address of the RAM drive, so it is
necessary to restore the original value after use.
Related I/O 1E8Eh
I/O 1E8Eh
Name Window selection
Undocumented
Function
[READ/WRITE]
Bit 7-0: Memory type controlled by DA00h bank
80h = ROM specification
81h = BANK RAM specification
84h = PCMCIA window specification
Explanation o Switches the contents of the DA bank
o This I/O is also used to specify the bank memory for the RAM drive, so it is
necessary to restore the original value after use.
Related I/O 0E8Eh
-------------------------------------------------------------------------------
■PCMCIA controller
Applicable PC-9821Np, Ns, Ne2, Nd, Es, Ld, Lt, Nf, Nm, Ne3, Nd2, Na7, Nx, Xa10/C12, PC-9801NL/A
PC-9821N-P02, PC-9801-102, PC-9821XA-E01, PC-9821XE-E01
Chip CL-PD6720
Explanation o These models use the CirrusLogic CL-PD6720 as the PCMCIA controller.
o The CL-PD6720 can only control up to two sockets per chip, so the CL-PD6720
is also used in the PCMCIA socket unit PC-9821N-P02 that is installed in the 98NOTE bay.
o The PCMCIA controller CL-PD6720 is connected to the user-open I/O addresses
of I/O 03E0h and 03E1h. Please note that on these PCMCIA-equipped models,
these addresses cannot be used by the user.
u I/O 03E0h and 03E1h are the same I/O addresses used by the PCMCIA controller
of IBM PC/AT-compatible machines.
o It is recommended that you use the socket service whenever possible to control the PCMCIA socket.
Related F8E8:0004h bit 0
I/O 03E0h
Name PCMCIA controller control [INDEX]
Undocumented
Function
[READ/WRITE]
bit 7: Device Index
0 = Built-in PCMCIA controller
1 = Expansion PCMCIA controller
bit 6: Socket Index
0 = Select socket #0/#2
1 = Select socket #1/#3
bit 5-0: Register Index
Explanation o Specifies the register number of the PCMCIA controller.
o Select the PCMCIA socket with bits 7 and 6. However, reading from this I/O
is only performed from the built-in PCMCIA controller. When an expansion
PCMCIA controller is specified, reading from this I/O is disabled.
Related I/O 03E1h
I/O 03E1h
Name PCMCIA controller control [DATA]
Undocumented
Function
[READ/WRITE]
Bits 7-0: Data input/output
---------+-----------------------------------------------
Register | Contents
---------+-----------------------------------------------
00h | Chip Revision
| * For PC-9821Np, Ns, Ne2, Nd, and Es, 82h is returned. This is also the same
| for the controller for the additional PCMCIA socket built into the 98NOTE bay.
01h | Interface Status
02h | Power Control
03h | Interrupt and General Control
04h | Card Status Change
05h | Management Interrupt Configuration
06h | Mapping Enable
07h | I/O Windows Control
08h | I/O Map 0 Start Address Low
09h | I/O Map 0 Start Address High
0Ah | I/O Map 0 End Address Low
0Bh | I/O Map 0 End Address High
0Ch | I/O Map 1 Start Address Low
0Dh | I/O Map 1 Start Address High
0Eh | I/O Map 1 End Address Low
0Fh | I/O Map 1 End Address High
---------+---------------------------------------------------
10h | Memory Map 0 Start Address Low
11h | Memory Map 0 Start Address High
12h | Memory Map 0 End Address Low
13h | Memory Map 0 End Address High
14h | Memory Map 0 Address Offset Low
15h | Memory Map 0 Address Offset High
16h | Misc Control 1
17h | FIFO Control
18h | Memory Map 1 Start Address Low
19h | Memory Map 1 Start Address High
1Ah | Memory Map 1 End Address Low
1Bh | Memory Map 1 End Address High
1Ch | Memory Map 1 Address Offset Low
1Dh | Memory Map 1 Address Offset High
1Eh | Misc Control 2
1Fh | Chip Information
---------+---------------------------------------------------
20h | Memory Map 2 Start Address Low
21h | Memory Map 2 Start Address High
22h | Memory Map 2 End Address Low
23h | Memory Map 2 End Address High
24h | Memory Map 2 Address Offset Low
25h | Memory Map 2 Address Offset High
26h | ATA Control
27h | Reserved
28h | Memory Map 3 Start Address Low
29h | Memory Map 3 Start Address High
2Ah | Memory Map 3 End Address Low
2Bh | Memory Map 3 End Address High
2Ch | Memory Map 3 Address Offset Low
2Dh | Memory Map 3 Address Offset High
2Eh | Extension Index
2Fh | Extension Data
---------+---------------------------------------------------
30h | Memory Map 4 Start Address Low
31h | Memory Map 4 Start Address High
32h | Memory Map 4 End Address Low
33h | Memory Map 4 End Address High
34h | Memory Map 4 Address Offset Low
35h | Memory Map 4 Address Offset High
36h | I/O Map 0 Address Offset Low
37h | I/O Map 0 Address Offset High
38h | I/O Map 1 Address Offset Low
39h | I/O Map 1 Address Offset High
3Ah | Setup Timing 0
3Bh | Command Timing 0
3Ch | Recovery Timing 0
3Dh | Setup Timing 1
3Eh | Command Timing 1
3Fh | Recovery Timing 1
---------+-----------------------------------------------
Explanation o I/O 03E0h Reads and writes the register specified by bits 5 to 0.
Related I/O 03E1h
-------------------------------------------------------------------------------